View MAX19713ETN_4136404.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-0529; Rev 1; 9/06
KIT ATION EVALU BLE AVAILA
10-Bit, 45Msps, Full-Duplex Analog Front-End
General Description Features
Dual 10-Bit, 45Msps Rx ADC and Dual 10-Bit, 45Msps Tx DAC Ultra-Low Power 91.8mW at fCLK = 45MHz, FD Mode 79.2mW at fCLK = 45MHz, Slow Rx Mode 49.5mW at fCLK = 45MHz, Slow Tx Mode Low-Current Standby and Shutdown Modes Programmable Tx DAC Common-Mode DC Level and I/Q Offset Trim Excellent Dynamic Performance SNR = 54.1dB at fIN = 5.5MHz (Rx ADC) SFDR = 70.3dBc at fOUT = 2.2MHz (Tx DAC) Three 12-Bit, 1s Aux-DACs 10-Bit, 333ksps Aux-ADC with 4:1 Input Mux and Data Averaging Excellent Gain/Phase Match 0.03 Phase, 0.02dB Gain (Rx ADC) at fIN = 5.5MHz Multiplexed Parallel Digital I/O Serial-Interface Control Versatile Power-Control Circuits Shutdown, Standby, Idle, Tx/Rx Disable Miniature 56-Pin Thin QFN Package (7mm x 7mm x 0.8mm)
MAX19713
The MAX19713 is an ultra-low-power, highly integrated mixed-signal analog front-end (AFE) ideal for wideband communication applications operating in full-duplex (FD) mode. Optimized for high dynamic performance and ultra-low power, the device integrates a dual 10-bit, 45Msps receive (Rx) ADC; dual 10-bit, 45Msps transmit (Tx) DAC; three fast-settling 12-bit aux-DAC channels for ancillary RF front-end control; and a 10-bit, 333ksps housekeeping aux-ADC. The typical operating power in FD mode is 91.8mW at a 45MHz clock frequency. The Rx ADCs feature 54dB SINAD and 72.2dBc SFDR at 5.5MHz input frequency with a 45MHz clock frequency. The analog I/Q input amplifiers are fully differential and accept 1.024VP-P full-scale signals. Typical I/Q channel matching is 0.03 phase and 0.02dB gain. The Tx DACs feature 70.3dBc SFDR at fOUT = 2.2MHz and fCLK = 45MHz. The analog I/Q full-scale output voltage range is 400mV differential. The output DC common-mode voltage is selectable from 0.71V to 1.06V. The I/Q channel offset is adjustable to optimize radio lineup sideband/carrier suppression. Typical I/Q channel matching is 0.01dB gain and 0.05 phase. Two independent 10-bit parallel, high-speed digital buses used by the Rx ADC and Tx DAC allow fullduplex operation for frequency-division duplex applications. The Rx ADC and Tx DAC can be disabled independently to optimize power management. A 3-wire serial interface controls power-management modes, the aux-DAC channels, and the aux-ADC channels. The MAX19713 operates on a single 2.7V to 3.3V analog supply and 1.8V to 3.3V digital I/O supply. The MAX19713 is specified for the extended (-40C to +85C) temperature range and is available in a 56-pin, thin QFN package. The Selector Guide at the end of the data sheet lists other pin-compatible versions in this AFE family. For time-division duplex (TDD) applications, refer to the MAX19705-MAX19708 AFE family of products.
Pin Configuration
CS/WAKE
TOP VIEW
ADC2 GND VDD VDD
DOUT
SCLK
DA9
DA8
DA7
DA6
DA5
42 41 40 39 38 37 36 35 34 33 32 31 30 29 ADC1 43 DAC3 44 DAC2 45 DAC1 46 VDD 47 IDN 48 IDP 49 GND 50 VDD 51 QDN 52 QDP 53 REFIN 54 EXPOSED PADDLE (GND) 28 DA3 27 DA2 26 DA1 25 DA0 24 OVDD 23 OGND 22 AD9
Applications
WiMAX CPEs 801.11a/b/g WLAN VoIP Terminals Portable Communication Equipment
MAX19713
DA4 21 AD8 20 AD7 19 AD6 18 AD5 17 AD4 16 AD3 15 AD2 AD1
Ordering Information
PART* MAX19713ETN MAX19713ETN+ PIN-PACKAGE 56 Thin QFN-EP** 56 Thin QFN-EP** PKG CODE T5677-1 T5677-1
COM 55 REFN 56 1 REFP 2 VDD 3 IAP 4 IAN
5 GND
6 CLK
DIN 7 GND
8 VDD
9 QAN
10 11 12 13 14 QAP VDD GND AD0
THIN QFN
NOTE: THE PIN 1 INDICATOR IS "+" FOR LEAD-FREE DEVICES.
*All devices are specified over the -40C to +85C operating range. **EP = Exposed paddle. +Denotes lead-free package.
Functional Diagram and Selector Guide appear at end of data sheet.
1
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
10-Bit, 45Msps, Full-Duplex Analog Front-End MAX19713
ABSOLUTE MAXIMUM RATINGS
VDD to GND, OVDD to OGND ..............................-0.3V to +3.6V GND to OGND.......................................................-0.3V to +0.3V IAP, IAN, QAP, QAN, IDP, IDN, QDP, QDN, DAC1, DAC2, DAC3 to GND .....................-0.3V to VDD ADC1, ADC2 to GND.................................-0.3V to (VDD + 0.3V) REFP, REFN, REFIN, COM to GND ...........-0.3V to (VDD + 0.3V) AD0-AD9, DA0-DA9, SCLK, DIN, CS/WAKE, CLK, DOUT to OGND .........................-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70C) 56-Pin Thin QFN-EP (derate 27.8mW/C above +70C) 2.22W Thermal Resistance JA ..................................................36C/W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33F, CL < 5pF on all aux-DAC outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER POWER REQUIREMENTS Analog Supply Voltage Output Supply Voltage VDD OVDD FD mode: fCLK = 45MHz, fOUT = 2.2MHz on both DAC channels; fIN = 5.5MHz on both ADC channels; auxDACs ON and at midscale, aux-ADC ON SPI2-Tx mode: fCLK = 45MHz, fOUT = 2.2MHz on both DAC channels; Rx ADC OFF; aux-DACs ON and at midscale, auxADC ON SPI1-Rx mode: fCLK = 45MHz, fIN = 5.5MHz on both ADC channels; Tx DAC OFF (Tx DAC outputs at 0V); aux-DACs ON and at midscale, aux-ADC ON SPI4-Tx mode: fCLK = 45MHz, fOUT = 2.2MHz on both DAC channels; Rx ADC ON (output tri-stated); aux-DACs ON and at midscale, aux-ADC ON SPI3-Rx mode: fCLK = 45MHz, fIN = 5.5MHz on both channels; Tx DAC ON (Tx DAC outputs at midscale); aux-DACs ON and at midscale, aux-ADC ON Standby mode: CLK = 0 or OVDD; aux-DACs ON and at midscale, aux-ADC ON 2.7 1.8 3.0 3.3 VDD V V SYMBOL CONDITIONS MIN TYP MAX UNITS
31.9
37
16.7
19
27.6
32 mA
VDD Supply Current
31.0
36
30.2
35
3.3
5
2
_______________________________________________________________________________________
10-Bit, 45Msps, Full-Duplex Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33F, CL < 5pF on all aux-DAC outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER SYMBOL CONDITIONS Idle mode: fCLK = 45MHz; aux-DACs ON and at midscale, aux-ADC ON VDD Supply Current Shutdown mode: CLK = 0 or OVDD, auxADC OFF FD mode: fCLK = 45MHz, fOUT = 2.2MHz on both DAC channels; fIN = 5.5MHz on both ADC channels; aux-DACs ON and at midscale, aux-ADC ON SPI1-Rx and SPI3-Rx modes: fCLK = 45MHz, fIN = 5.5MHz on both ADC channels; DAC input bus tri-stated; auxDACs ON and at midscale, aux-ADC ON OVDD Supply Current SPI2-Tx and SPI4-Tx modes: fCLK = 45MHz, fOUT = 2.2MHz on both DAC channels; ADC output bus tri-stated; auxDACs ON and at midscale, aux-ADC ON Standby mode: CLK = 0 or OVDD; auxDACs ON and at midscale, aux-ADC ON Idle mode: fCLK = 45MHz; aux-DACs ON and at midscale, aux-ADC ON Shutdown mode: CLK = 0 or OVDD, auxADC OFF Rx ADC DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error DC Gain Matching Offset Matching Gain Temperature Coefficient Power-Supply Rejection Rx ADC ANALOG INPUT Input Differential Range Input Common-Mode Voltage Range Input Impedance VID VCM RIN CIN Switched capacitor load Differential or single-ended inputs 0.512 VDD / 2 120 5 V V k pF Offset (VDD 5%) Gain (VDD 5%) INL DNL Residual DC offset error Includes reference error -5 -5 -0.15 10 1.25 0.65 0.2 0.7 0.04 10 30 0.2 0.07 +5 +5 +0.15 Bits LSB LSB %FS %FS dB LSB ppm/C LSB MIN TYP 12.4 0.5 MAX 15 5 UNITS mA A
MAX19713
4.6 mA 4.35
310
0.1 73 0.1
A
_______________________________________________________________________________________
3
10-Bit, 45Msps, Full-Duplex Analog Front-End MAX19713
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33F, CL < 5pF on all aux-DAC outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Rx ADC CONVERSION RATE Maximum Clock Frequency Data Latency Rx ADC DYNAMIC CHARACTERISTICS (Note 3) Signal-to-Noise Ratio Signal-to-Noise and Distortion Spurious-Free Dynamic Range Total Harmonic Distortion Third-Harmonic Distortion Intermodulation Distortion Third-Order Intermodulation Distortion Aperture Delay Aperture Jitter Overdrive Recovery Time Rx ADC INTERCHANNEL CHARACTERISTICS Crosstalk Rejection Amplitude Matching Phase Matching Tx DAC DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Residual DC Offset Full-Scale Gain Error N INL DNL VOS Guaranteed monotonic (Note 6) -0.7 -4 -40 10 0.35 0.2 0.1 +0.7 +4 +40 Bits LSB LSB mV mV fINX,Y = 5.5MHz, AINX,Y = -0.5dBFS, fINY,X = 1.8MHz, AINY,X = -0.5dBFS (Note 4) fIN = 5.5MHz, AIN = -0.5dBFS (Note 5) fIN = 5.5MHz, AIN = -0.5dBFS (Note 5) -88 0.02 0.03 dB dB Degrees 1.5x full-scale input SNR SINAD SFDR THD HD3 IMD IM3 fIN = 5.5MHz fIN = 19.4MHz fIN = 5.5MHz fIN = 19.4MHz fIN = 5.5MHz fIN = 19.4MHz fIN = 5.5MHz fIN = 19.4MHz fIN = 5.5MHz fIN = 19.4MHz fIN1 = 1.8MHz, AIN1 = -7dBFS; fIN2 = 1.0MHz, AIN2 = -7dBFS fIN1 = 1.8MHz, AIN1 = -7dBFS; fIN2 = 1.0MHz, AIN2 = -7dBFS 63 52.4 52.7 54.5 54 54.3 53.9 72.1 76.3 -69.4 -71.3 -73.7 -76.3 -69 -72 3.5 2 2 -61 dB dB dBc dBc dBc dBc dBc ns psRMS ns fCLK (Note 2) Channel IA Channel QA 5 5.5 45 MHz Clock Cycles SYMBOL CONDITIONS MIN TYP MAX UNITS
4
_______________________________________________________________________________________
10-Bit, 45Msps, Full-Duplex Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33F, CL < 5pF on all aux-DAC outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Tx DAC DYNAMIC PERFORMANCE DAC Conversion Rate In-Band Noise Density Third-Order Intermodulation Distortion Glitch Impulse Spurious-Free Dynamic Range to Nyquist Total Harmonic Distortion to Nyquist Signal-to-Noise Ratio to Nyquist SFDR THD SNR fOUT = 2.2MHz fOUT = 2.2MHz fOUT = 2.2MHz fOUTX,Y = 500kHz, fOUTY,X = 620kHz Measured at DC fOUT = 2.2MHz -0.4 61.5 SYMBOL fCLK ND IM3 (Note 2) fOUT = 2.2MHz fOUT1 = 2MHz, fOUT2 = 2.2MHz -129 -82 10 70.3 -68.1 56.1 -60.5 CONDITIONS MIN TYP MAX 45 UNITS MHz dBFS/Hz dBc pV*s dBc dBc dB
MAX19713
Tx DAC INTERCHANNEL CHARACTERISTICS I-to-Q Output Isolation Gain Mismatch Between I and Q Channels Phase Mismatch Between I and Q Channels Differential Output Impedance Tx DAC ANALOG OUTPUT Full-Scale Output Voltage 85 0.01 0.05 800 VFS Bits CM1 = 0, CM0 = 0 (default) Output Common-Mode Voltage VCOMD Bits CM1 = 0, CM0 = 1 Bits CM1 = 1, CM0 = 0 Bits CM1 = 1, CM0 = 1 Rx ADC-Tx DAC INTERCHANNEL CHARACTERISTICS Receive Transmit Isolation AUXILIARY ADCs (ADC1, ADC2) Resolution Full-Scale Reference Analog Input Range Analog Input Impedance Input-Leakage Current Gain Error Zero-Code Error Differential Nonlinearity GE ZE DNL Measured at DC Measured at unselected input from 0 to VREF Includes reference error, AD1 = 0 -5 2 0.6 ADC: fINI = fINQ = 5.5MHz, DAC: fOUTI = fOUTQ = 2.2MHz N VREF AD1 = 0 (default) AD1 = 1 10 2.048 VDD 0 to VREF 500 0.1 +5 85 dB 1.01 0.88 0.75 0.62 400 1.06 0.94 0.82 0.71 1.11 1.00 0.90 0.81 V +0.4 dB dB Degrees
mV
Bits V V k A %FS mV LSB
_______________________________________________________________________________________
5
10-Bit, 45Msps, Full-Duplex Analog Front-End MAX19713
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33F, CL < 5pF on all aux-DAC outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Integral Nonlinearity Supply Current AUXILIARY DACs (DAC1, DAC2, DAC3) Resolution Integral Nonlinearity Differential Nonlinearity Output-Voltage Low Output-Voltage High DC Output Impedance Settling Time Glitch Impulse Rx ADC-Tx DAC TIMING CHARACTERISTICS CLK Rise to Channel-I Output Data Valid CLK Fall to Channel-Q Output Data Valid I-DAC DATA to CLK Fall Setup Time Q-DAC DATA to CLK Rise Setup Time CLK Fall to I-DAC Data Hold Time CLK Rise to Q-DAC Data Hold Time CLK Duty Cycle CLK Duty-Cycle Variation Digital Output Rise/Fall Time Falling Edge of CS/WAKE to Rising Edge of First SCLK Time DIN to SCLK Setup Time DIN to SCLK Hold Time SCLK Pulse-Width High SCLK Pulse-Width Low SCLK Period SCLK to CS/WAKE Setup Time
CS/WAKE High Pulse Width CS/WAKE High to DOUT Active High
SYMBOL INL
CONDITIONS
MIN
TYP 0.6 210
MAX
UNITS LSB A Bits
N INL DNL VOL VOH From code 100 to code 4000 Guaranteed monotonic over code 100 to code 4000 (Note 6) RL > 200k RL > 200k DC output at midscale From code 1024 to code 3072, within 10 LSB From code 0 to code 4095
12 1.25 -1.0 0.65 +1.2 0.2 2.57 4 1 24
LSB LSB V V
s nV*s
tDOI tDOQ tDSI tDSQ tDHI tDHQ
Figure 3 (Note 6) Figure 3 (Note 6) Figure 5 (Note 6) Figure 5 (Note 6) Figure 5 (Note 6) Figure 5 (Note 6)
5.5 6.5 10 10 0 0
8.2 9.5
12.5 13.6
ns ns ns ns ns ns
50 10 20% to 80% 2.4
% % ns
SERIAL-INTERFACE TIMING CHARACTERISTICS (Figures 6 and 8, Note 6) tCSS tDS tDH tCH tCL tCP tCS tCSW tCSD Bit AD0 set 10 10 0 25 25 50 10 80 200 ns ns ns ns ns ns ns ns ns
6
_______________________________________________________________________________________
10-Bit, 45Msps, Full-Duplex Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33F, CL < 5pF on all aux-DAC outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER
CS/WAKE High to DOUT Low (Aux-ADC Conversion Time)
MAX19713
SYMBOL tCONV tDCS tCD tCHZ
CONDITIONS Bit AD0 set, no averaging, fCLK = 45MHz, CLK divider = 16 Bit AD0, AD10 set Bit AD0, AD10 set Bit AD0, AD10 set
MIN
TYP 4.3 200
MAX
UNITS s ns
DOUT Low to CS/WAKE Setup Time SCLK Low to DOUT Data Out
CS/WAKE High to DOUT High Impedance
14.5 200
ns ns
MODE-RECOVERY TIMING CHARACTERISTICS (Figure 7) From shutdown to Rx mode, ADC settles to within 1dB SINAD From shutdown to Tx mode, DAC settles to within 10 LSB error Shutdown Wake-Up Time tWAKE,SD From aux-ADC enable to aux-ADC start conversion From shutdown to aux-DAC output valid From shutdown to FD mode, ADC settles to within 1dB SINAD, DAC settles to within 10 LSB error From idle to Rx mode with CLK present during idle, ADC settles to within 1dB SINAD Idle Wake-Up Time (With CLK) tWAKE,ST0 From idle to Tx mode with CLK present during idle, DAC settles to 10 LSB error From idle to FD mode, ADC settles to within 1dB SINAD, DAC settles to within 10 LSB error From standby to Rx mode, ADC settles to within 1dB SINAD Standby Wake-Up Time tWAKE,ST1 From standby to Tx mode, DAC settles to 10 LSB error From standby to FD mode, ADC settles to within 1dB SINAD, DAC settles to within 10 LSB error Enable Time from Tx to Rx, Fast Mode Enable Time from Rx to Tx, Fast Mode Enable Time from Tx to Rx, Slow Mode tENABLE,RX tENABLE,TX tENABLE,RX ADC settles to within 1dB SINAD DAC settles to within 10 LSB error ADC settles to within 1dB SINAD 500 26.4 10 28 500 s
3.7 5.1
s
5.1
3.8 24.4
s
24.4
0.1 0.1 3.7
s s s
_______________________________________________________________________________________
7
10-Bit, 45Msps, Full-Duplex Analog Front-End MAX19713
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33F, CL < 5pF on all aux-DAC outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Enable Time from Rx to Tx, Slow Mode Positive Reference Negative Reference Common-Mode Output Voltage Maximum REFP/REFN/COM Source Current Maximum REFP/REFN/COM Sink Current Differential Reference Output Differential Reference Temperature Coefficient Reference Input Voltage Differential Reference Output Common-Mode Output Voltage Maximum REFP/REFN/COM Source Current Maximum REFP/REFN/COM Sink Current REFIN Input Current REFIN Input Resistance DIGITAL INPUTS (CLK, SCLK, DIN, CS/WAKE, DA9-DA0) Input High Threshold Input Low Threshold VINH VINL CLK, SCLK, DIN, CS/WAKE = OGND or OVDD DA9-DA0 = OVDD DA9-DA0 = OGND Input Capacitance DIGITAL OUTPUTS (AD9-AD0, DOUT) Output-Voltage Low Output-Voltage High Tri-State Leakage Current Tri-State Output Capacitance VOL VOH ILEAK COUT ISINK = 200A ISOURCE = 200A 0.8 x OVDD -1 5 +1 0.2 x OVDD V V A pF DCIN -1 -1 -5 5 0.7 x OVDD 0.3 x OVDD +1 +1 +5 pF A V V VCOM ISOURCE ISINK VREF REFTC VREFP - VREFN +0.490 SYMBOL tENABLE,TX CONDITIONS DAC settles to within 10 LSB error MIN TYP 4.9 MAX UNITS s
INTERNAL REFERENCE (VREFIN = VDD; VREFP, VREFN, VCOM levels are generated internally) VREFP - VCOM VREFN - VCOM 0.256 -0.256 VDD / 2 VDD / 2 VDD / 2 - 0.15 + 0.15 2 2 +0.512 30 +0.534 V V V mA mA V ppm/C
BUFFERED EXTERNAL REFERENCE (external VREFIN = 1.024V applied; VREFP, VREFN, VCOM levels are generated internally) VREFIN VDIFF VCOM ISOURCE ISINK VREFP - VREFN 1.024 0.512 VDD / 2 2 2 -0.7 500 V V V mA mA A k
Input Leakage
DIIN
8
_______________________________________________________________________________________
10-Bit, 45Msps, Full-Duplex Analog Front-End MAX19713
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33F, CL < 5pF on all aux-DAC outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
Note 1: Specifications from TA = +25C to +85C guaranteed by production tests. Specifications at TA < +25C guaranteed by design and characterization. Note 2: The minimum clock frequency (fCLK) for the MAX19713 is 7.5MHz (typ). The minimum aux-ADC sample rate clock frequency (ACLK) is determined by fCLK and the chosen aux-ADC clock-divider value. The minimum aux-ADC ACLK > 7.5MHz / 128 = 58.6kHz. The aux-ADC conversion time does not include the time to clock the serial data out of DOUT. The maximum conversion time (for no averaging, NAVG = 1) will be tCONV (max) = (12 x 1 x 128) / 7.5MHz = 205s. Note 3: SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dBFS referenced to the amplitude of the digital outputs. SINAD and THD are calculated using HD2 through HD6. Note 4: Crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the second channel. FFTs are performed on each channel. The parameter is specified as the power ratio of the first and second channel FFT test tones. Note 5: Amplitude and phase matching are measured by applying the same signal to each channel, and comparing the two output signals using a sine-wave fit. Note 6: Guaranteed by design and characterization.
Typical Operating Characteristics
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33F, TA = +25C, unless otherwise noted.)
Rx ADC CHANNEL-IA FFT PLOT (8192 SAMPLES)
MAX19713 toc01
Rx ADC CHANNEL-QA FFT PLOT (8192 SAMPLES)
FUNDAMENTAL fIN = 13.024292MHz AIN = -0.48dBFS SINAD = 54.216dB SNR = 54.302dB SFDR = 76dBc THD = -71.311dBc 2 6
MAX19713 toc02
Rx ADC CHANNEL-IA TWO-TONE FFT PLOT
-10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 2fIN1 - fIN2 2fIN2 - fIN1 fIN1 fIN2 fIN1 = 1.7605591MHz fIN2 = 1.8484497MHz AIN1 = AIN2 = -7dBFS IMD = -65dBc
MAX19713 toc03
0 -10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 0
FUNDAMENTAL fIN = 13.024292MHz AIN = -0.488dBFS SINAD = 53.763dB SNR = 54.003dB SFDR = 71.6dBc THD = -66.46dBc 3 6 2
0 -10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 -100
0
4
5
34
5
5
10
15
20
0
5
FREQUENCY (MHz)
10 15 FREQUENCY (MHz)
20
0
5
10 15 FREQUENCY (MHz)
20
_______________________________________________________________________________________
9
10-Bit, 45Msps, Full-Duplex Analog Front-End MAX19713
Typical Operating Characteristics (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33F, TA = +25C, unless otherwise noted.)
Rx ADC CHANNEL-QA TWO-TONE FFT PLOT
-10 -20 AMPLITUDE (dBFS) -30 SNR (dB) -40 -50 -60 -70 -80 -90 -100 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 FREQUENCY (MHz) 51 50 0 10 20 30 40 50 60 70 80 90 100 ANALOG INPUT FREQUENCY (MHz) 51 50 0 10 20 30 40 50 60 70 80 90 100 ANALOG INPUT FREQUENCY (MHz) 2fIN1 - fIN2 2fIN2 - fIN1 fIN1 fIN2 fIN1 = 1.7605591MHz fIN2 = 1.8484497MHz AIN1 = AIN2 = -7dBFS IMD = -66dBc
MAX19713 toc04
Rx ADC SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY
MAX19713 toc05
Rx ADC SIGNAL-TO-NOISE AND DISTORTION RATIO vs. ANALOG INPUT FREQUENCY
MAX19713 toc06
0
57 56 55 54 53 IA 52 QA
57 56 55 SINAD (dB) 54 53 52 IA QA
Rx ADC TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY
MAX19713 toc07
Rx ADC SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY
MAX19713 toc08
Rx ADC SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT AMPLITUDE
fIN = 13.057251MHz 55 50 QA
MAX19713 toc09
90 85 80 -THD (dBc)
90 85 80
60
SFDR (dBc)
75 70 65 60
QA 75 70 65 60 IA 55 50 0 10 20 30 40 50 60 70 80 90 100 ANALOG INPUT FREQUENCY (MHz) 0 IA
QA SNR (dB)
45 40 35 30 25 20 -30 -25 -20 -15 -10 -5 0 IA
55 50
10 20 30 40 50 60 70 80 90 100 ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT AMPLITUDE (dBFS)
Rx ADC SIGNAL-TO-NOISE AND DISTORTION RATIO vs. ANALOG INPUT AMPLITUDE
MAX19713 toc10
Rx ADC TOTAL HARMONIC DISTORTION vs. ANALOG INPUT AMPLITUDE
75 70 65 -THD (dBc) 60 55 50 45 40 35 30 IA QA fIN = 13.057251MHz
MAX19713 toc11
60 fIN = 13.057251MHz 55 50 SINAD (dB) 45 40 35 30 25 20 -30 -25 -20 -15 -10 -5 0 ANALOG INPUT AMPLITUDE (dBFS) IA QA
80
-30
-25
-20
-15
-10
-5
0
ANALOG INPUT AMPLITUDE (dBFS)
10
______________________________________________________________________________________
10-Bit, 45Msps, Full-Duplex Analog Front-End MAX19713
Typical Operating Characteristics (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33F, TA = +25C, unless otherwise noted.)
Rx ADC SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT AMPLITUDE
MAX19713 toc12
Rx ADC SIGNAL-TO-NOISE RATIO vs. SAMPLING FREQUENCY
MAX19713 toc13
Rx ADC SIGNAL-TO-NOISE AND DISTORTION RATIO vs. SAMPLING FREQUENCY
56.5 56.0 55.5 SINAD (dB) 55.0 54.5 54.0 53.5 53.0 52.5 52.0 IA QA fIN = 13.024292MHz
MAX19713 toc14
80 75 70 65 SFDR (dBc)
fIN = 13.057251MHz
57.0 56.5 56.0 55.5 SNR (dB) 55.0 54.5 54.0 53.5 53.0 52.5 52.0
fIN = 13.024292MHz
57.0
QA
60 55 50 45 40 35 30 -30 -25 -20 -15 -10 -5 0 ANALOG INPUT AMPLITUDE (dBFS) IA QA
IA
5
10
15
20
25
30
35
40
45
5
10
15
20
25
30
35
40
45
SAMPLING FREQUENCY (MHz)
SAMPLING FREQUENCY (MHz)
Rx ADC TOTAL HARMONIC DISTORTION vs. SAMPLING FREQUENCY
MAX19713 toc15
Rx ADC SPURIOUS-FREE DYNAMIC RANGE vs. SAMPLING FREQUENCY
fIN = 13.024292MHz
MAX19713 toc16
85 80 75 -THD (dBc) 70 65
90 85 80 SFDR (dBc) 75 70 65 60 55
fIN = 13.024292MHz
QA
QA
IA
IA 60 55 5 10 15 20 25 30 35 40 45 SAMPLING FREQUENCY (MHz)
5
10
15
20
25
30
35
40
45
SAMPLING FREQUENCY (MHz)
Rx ADC SIGNAL-TO-NOISE RATIO vs. CLOCK DUTY CYCLE
MAX19713 toc17
Rx ADC SIGNAL-TO-NOISE AND DISTORTION RATIO vs. CLOCK DUTY CYCLE
62.5 60.0 57.5 SINAD (dB) 55.0 52.5 50.0 47.5 45.0 42.5 40.0 QA IA fIN = 13.024292MHz
MAX19713 toc18
65.0 62.5 60.0 57.5 SNR (dB) 55.0 52.5 50.0 47.5 45.0 42.5 40.0
fIN = 13.024292MHz IA
65.0
QA
40
45
50
55
60
40
45
50
55
60
CLOCK DUTY CYCLE (%)
CLOCK DUTY CYCLE (%)
______________________________________________________________________________________
11
10-Bit, 45Msps, Full-Duplex Analog Front-End MAX19713
Typical Operating Characteristics (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33F, TA = +25C, unless otherwise noted.)
Rx ADC TOTAL HARMONIC DISTORTION vs. CLOCK DUTY CYCLE
100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 fIN = 13.024292MHz QA 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30
MAX19713 toc19
Rx ADC SPURIOUS-FREE DYNAMIC RANGE vs. CLOCK DUTY CYCLE
MAX19713 toc20
Rx ADC OFFSET ERROR vs. TEMPERATURE
0.75 OFFSET ERROR (%FS) 0.50 0.25 0 -0.25 -0.50 IA -0.75 -1.00 QA
MAX19713 toc21
fIN = 13.024292MHz
1.00
SFDR (dBc)
-THD (dBc)
QA
IA
IA
40
45
50
55
60
40
45
50
55
60
-40
-15
CLOCK DUTY CYCLE (%)
CLOCK DUTY CYCLE (%)
10 35 TEMPERATURE (C)
60
85
Rx ADC GAIN ERROR vs. TEMPERATURE
MAX19713 toc22
Tx DAC SPURIOUS-FREE DYNAMIC RANGE vs. SAMPLING FREQUENCY
fOUT = fCLK / 10 85 80 QD SFDR (dBc)
MAX19713 toc23
Tx DAC SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY
MAX19713 toc24
2.00 1.75 1.50 GAIN ERROR (%FS) QA 1.00 0.75 0.50 0.25 0 -40 -15 IA 10 35 TEMPERATURE (C) 60
90
80 75 70 65 60 ID 55 QD
SFDR (dBc)
1.25
75 70 65 60 55 ID
50 45
85
5
10
15
20
25
30
35
40
45
0
2
4
6
8
10 12 14 16 18 20 22
SAMPLING FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
Tx DAC SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT AMPLITUDE
MAX19713 toc25
Tx DAC CHANNEL-ID SPECTRAL PLOT
MAX19713 toc26
Tx DAC CHANNEL-QD SPECTRAL PLOT
-10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 HD3 fOUT = 5.498MHz
MAX19713 toc27
90 fOUT = 5.498MHz 80 70 SFDR (dBc) 60 50 40 30 -30 -25 -20 -15 -10 -5 0 OUTPUT AMPLITUDE (dBFS) ID QD
0 -10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 0 HD3 fOUT = 5.498MHz
0
2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 FREQUENCY (MHz)
0
2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 FREQUENCY (MHz)
12
______________________________________________________________________________________
10-Bit, 45Msps, Full-Duplex Analog Front-End MAX19713
Typical Operating Characteristics (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33F, TA = +25C, unless otherwise noted.)
Tx DAC CHANNEL-ID TWO-TONE SPECTRAL PLOT
MAX19713 toc28
Tx DAC CHANNEL-QD TWO-TONE SPECTRAL PLOT
MAX19713 toc29
SUPPLY CURRENT vs. SAMPLING FREQUENCY
fIN = 13.024292MHz, fOUT = 5.498MHz, FD MODE
MAX19713 toc30
0 -10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 0 fOUT1 = 4MHz, fOUT2 = 4.5MHz
0 -10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 fOUT1 = 4MHz, fOUT2 = 4.5MHz
40
35
IVDD (mA) 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 FREQUENCY (MHz)
30
25
20
15 5 10 15 20 25 30 35 40 45 SAMPLING FREQUENCY (MHz)
2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 FREQUENCY (MHz)
Rx ADC INTEGRAL NONLINEARITY
1.50 1.25 1.00 0.75 0.50 0.25 0 -0.25 -0.50 -0.75 -1.00 -1.25 -1.50 0 128 256 384 512 640 768 896 1024 DIGITAL OUTPUT CODE INL (LSB)
MAX19713 toc31
Rx ADC DIFFERENTIAL NONLINEARITY
0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 128 256 384 512 640 768 896 1024 DIGITAL OUTPUT CODE -0.6 -0.8 0 0.2 0 -0.2 -0.4
MAX19713 toc32
Tx DAC INTEGRAL NONLINEARITY
0.6 0.4
MAX19713 toc33
1.0
0.8
128 256 384 512 640 768 896 1024 DIGITAL INPUT CODE
Tx DAC DIFFERENTIAL NONLINEARITY
0.6 0.5 0.4 0.3 0.2 DNL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 0 128 256 384 512 640 768 896 1024 DIGITAL INPUT CODE
MAX19713 toc34
REFERENCE OUTPUT VOLTAGE vs. TEMPERATURE
MAX19713 toc35
AUX-DAC INTEGRAL NONLINEARITY
1.5 1.0 INL (LSB) 0.5 0 -0.5
MAX19713 toc36
0.520 VREFP - VREFN 0.515 VREFP - VREFN (V)
2.0
0.510
0.505
-1.0 -1.5
0.500 -40 -15 10 35 TEMPERATURE (C) 60 85
-2.0 0 512 1024 1536 2048 2560 3072 3584 4096 DIGITAL INPUT CODE
______________________________________________________________________________________
13
10-Bit, 45Msps, Full-Duplex Analog Front-End MAX19713
Typical Operating Characteristics (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33F, TA = +25C, unless otherwise noted.)
AUX-DAC DIFFERENTIAL NONLINEARITY
0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096 DIGITAL INPUT CODE -1.5 0 128 256 384 512 640 768 896 1024 DIGITAL OUTPUT CODE
MAX19713 toc37
AUX-ADC INTEGRAL NONLINEARITY
MAX19713 toc38
1.0
1.5 1.0 0.5 0 -0.5 -1.0
AUX-ADC DIFFERENTIAL NONLINEARITY
MAX19713 toc39
AUX-DAC OUTPUT VOLTAGE vs. OUTPUT SOURCE CURRENT
MAX19713 toc40
0.8 0.6 0.4
3.0 2.5 OUTPUT VOLTAGE (V) 2.0 1.5 1.0 0.5 0 0.001
DNL (LSB)
0.2 0 -0.2 -0.4 -0.6 -0.8 0 128 256 384 512 640 768 896 1024 DIGITAL OUTPUT CODE
0.01
0.1
1
10
100
OUTPUT SOURCE CURRENT (mA)
AUX-DAC OUTPUT VOLTAGE vs. OUTPUT SINK CURRENT
MAX19713 toc41
AUX-DAC SETTLING TIME
MAX19713 toc42
3.0 2.5 OUTPUT VOLTAGE (V) 2.0 1.5 1.0 0.5 0 0.001
STEP FROM CODE 1024 TO CODE 3072 1V/div
AUX-DAC OUTPUT
500mV/div
CS/WAKE 0.01 0.1 1 10 100 400ns/div
OUTPUT SINK CURRENT (mA)
14
______________________________________________________________________________________
10-Bit, 45Msps, Full-Duplex Analog Front-End
Pin Description
PIN 1 2, 8, 11, 39, 41, 47, 51 3 4 5, 7, 12, 40, 50 6 9 10 13-22 23 24 25-34 35 36 37 38 42 43 44 45 46 48 49 52 53 54 55 56 -- NAME REFP VDD IAP IAN GND CLK QAN QAP AD0-AD9 OGND OVDD DA0-DA9 DOUT DIN SCLK CS/WAKE ADC2 ADC1 DAC3 DAC2 DAC1 IDN IDP QDN QDP REFIN COM REFN EP FUNCTION Positive Reference Voltage Input Terminal. Bypass with a 0.33F capacitor to GND as close to REFP as possible. Analog Supply Voltage. Bypass VDD to GND with a combination of a 2.2F capacitor in parallel with a 0.1F capacitor. Channel-IA Positive Analog Input. For single-ended operation, connect signal source to IAP. Channel-IA Negative Analog Input. For single-ended operation, connect IAN to COM. Analog Ground. Connect all GND pins to ground plane. Conversion Clock Input. Clock signal for both receive ADCs and transmit DACs. Channel-QA Negative Analog Input. For single-ended operation, connect QAN to COM. Channel-QA Positive Analog Input. For single-ended operation, connect signal source to QAP. Receive ADC Digital Outputs. AD9 is the most significant bit (MSB) and AD0 is the least significant bit (LSB). Output-Driver Ground Output-Driver Power Supply. Supply range from +1.8V to VDD. Bypass OVDD to OGND with a combination of a 2.2F capacitor in parallel with a 0.1F capacitor. Transmit DAC Digital Inputs. DA9 is the most significant bit (MSB) and DA0 is the least significant bit (LSB). DA0-DA9 are internally pulled up to OVDD. Aux-ADC Digital Output 3-Wire Serial-Interface Data Input. Data is latched on the rising edge of SCLK. 3-Wire Serial-Interface Clock Input 3-Wire Serial-Interface Chip-Select/WAKE Input. When the MAX19713 is in shutdown, CS/WAKE controls the wake-up function. See the Wake-Up Function section. Selectable Auxiliary ADC Analog Input 2 Selectable Auxiliary ADC Analog Input 1 Auxiliary DAC3 Analog Output (VOUT = 0 at Power-Up) Auxiliary DAC2 Analog Output (VOUT = 0 at Power-Up) Auxiliary DAC1 Analog Output (AFC DAC, VOUT = 1.1V at Power-Up) Tx DAC Channel-ID Differential Negative Output Tx DAC Channel-ID Differential Positive Output Tx DAC Channel-QD Differential Negative Output Tx DAC Channel-QD Differential Positive Output Reference Input. Connect to VDD for internal reference. Common-Mode Voltage I/O. Bypass COM to GND with a 0.33F capacitor. Negative Reference Voltage Input Terminal. Rx ADC conversion range is (VREFP - VREFN). Bypass REFN to GND with a 0.33F capacitor. Exposed Paddle. Exposed paddle is internally connected to GND. Connect EP to the GND plane.
MAX19713
Detailed Description
The MAX19713 integrates a dual, 10-bit Rx ADC and a dual, 10-bit Tx DAC while providing ultra-low power and high dynamic performance at 45Msps conversion
rate. The Rx ADC analog input amplifiers are fully differential and accept 1.024VP-P full-scale signals. The Tx DAC analog outputs are fully differential with 400mV full-scale output, selectable common-mode DC level, and adjustable channel ID-QD offset trim.
15
______________________________________________________________________________________
10-Bit, 45Msps, Full-Duplex Analog Front-End MAX19713
The MAX19713 integrates three 12-bit auxiliary DACs (aux-DACs) and a 10-bit, 333ksps auxiliary ADC (auxADC) with 4:1 input multiplexer. The aux-DAC channels feature 1s settling time for fast AGC, VGA, and AFC level setting. The aux-ADC features data averaging to reduce processor overhead and a selectable clockdivider to program the conversion rate. The MAX19713 includes a 3-wire serial interface to control operating modes and power management. The serial interface is SPITM and MICROWIRETM compatible. The MAX19713 serial interface selects shutdown, idle, standby, FD, transmit (Tx), and receive (Rx) modes, as well as controls aux-DAC and aux-ADC channels. The MAX19713 features two independent, high-speed, 10-bit buses for the Rx ADC and Tx DAC, which allow full-duplex (FD) operation for frequency-division duplex applications. Each bus can be disabled to optimize power management through the 3-wire interface. The
MICROWIRE is a trademark of National Semiconductor Corp. SPI is a trademark of Motorola, Inc.
MAX19713 operates from a single 2.7V to 3.3V analog supply and a 1.8V to 3.3V digital supply.
Dual 10-Bit Rx ADC
The ADC uses a seven-stage, fully differential, pipelined architecture that allows for high-speed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half clock cycle. Including the delay through the output latch, the total clock-cycle latency is 5 clock cycles for channel IA and 5.5 clock cycles for channel QA. The ADC full-scale analog input range is VREF with a VDD / 2 (0.8V) common-mode input range. VREF is the difference between VREFP and VREFN. See the Reference Configurations section for details.
Input Track-and-Hold (T/H) Circuits Figure 1 displays a simplified diagram of the Rx ADC input track-and-hold (T/H) circuitry. Both ADC inputs (IAP, QAP, IAN, and QAN) can be driven either differentially or single-ended. Match the impedance of IAP and
INTERNAL BIAS S2a C1a S4a IAP C2a S4c S1
COM S5a S3a
OUT
IAN S4b C2b C1b S3b S2b INTERNAL BIAS INTERNAL BIAS S2a C1a S4a QAP C2a S4c S1 S5b COM
OUT
HOLD TRACK
HOLD TRACK
CLK INTERNAL NONOVERLAPPING CLOCK SIGNALS
COM S5a S3a
OUT
MAX19713
OUT
QAN S4b C2b C1b S3b S2b INTERNAL BIAS S5b COM
Figure 1. Rx ADC Internal T/H Circuits
16 ______________________________________________________________________________________
10-Bit, 45Msps, Full-Duplex Analog Front-End MAX19713
Table 1. Rx ADC Output Codes vs. Input Voltage
DIFFERENTIAL INPUT VOLTAGE VREF x 512/512 VREF x 511/512 VREF x 1/512 VREF x 0/512 -VREF x 1/512 -VREF x 511/512 -VREF x 512/512 DIFFERENTIAL INPUT (LSB) 511 (+Full Scale - 1 LSB) 510 (+Full Scale - 2 LSB) +1 0 (Bipolar Zero) -1 -511 (-Full Scale + 1 LSB) -512 (-Full Scale) OFFSET BINARY (AD0-AD9) 11 1111 1111 11 1111 1110 10 0000 0001 10 0000 0000 01 1111 1111 00 0000 0001 00 0000 0000 OUTPUT DECIMAL CODE 1023 1022 513 512 511 1 0
1 LSB =
2 x VREF 1024 VREF
VREF = VREFP - VREFN VREF
edge of CLK. Including the delay through the output latch, the total clock-cycle latency is 5 clock cycles for channel IA and 5.5 clock cycles for channel QA.
OFFSET BINARY OUTPUT CODE (LSB)
10 0000 0001 10 0000 0000 01 1111 1111
00 0000 0011 00 0000 0010 00 0000 0001 00 0000 0000
-512 -511 -510 -509
-1 0+ 1 (COM) INPUT VOLTAGE (LSB)
+509 +510 +511 +512
Figure 2. Rx ADC Transfer Function
VREF
VREF
11 1111 1111 11 1111 1110 11 1111 1101
(COM)
Digital Output Data (AD0-AD9) AD0-AD9 are the Rx ADC digital logic outputs of the MAX19713. The logic level is set by OVDD from 1.8V to VDD. The digital output coding is offset binary (Table 1). Keep the capacitive load on the digital outputs AD0-AD9 as low as possible (< 15pF) to avoid large digital currents feeding back into the analog portion of the MAX19713 and degrading its dynamic performance. Buffers on the digital outputs isolate the outputs from heavy capacitive loads. Adding 100 resistors in series with the digital outputs close to the MAX19713 will help improve ADC performance. Refer to the MAX19713EVKIT schematic for an example of the digital outputs driving a digital buffer through 100 series resistors. During SHDN, IDLE, STBY, SPI2, and SPI4 states, digital outputs AD0-AD9 are tri-stated.
Dual 10-Bit Tx DACs
IAN, as well as QAP and QAN, and set the input signal common-mode voltage within the VDD / 2 (0.8V) Rx ADC range for optimum performance. The dual 10-bit digital-to-analog converters (Tx DACs) operate with clock speeds up to 45MHz. The Tx DAC digital inputs, DA0-DA9, are multiplexed on a single 10-bit transmit bus. The voltage reference determines the Tx DAC full-scale voltage at IDP, IDN and QDP, QDN analog outputs. See the Reference Configurations section for setting the reference voltage.
Rx ADC System Timing Requirements Figure 3 shows the relationship between the clock, analog inputs, and the resulting output data. Channels IA and QA are sampled on the rising edge of the clock signal (CLK) and the resulting data is multiplexed at the AD0-AD9 outputs. Channel IA data is updated on the rising edge and channel QA data is updated on the falling
______________________________________________________________________________________
17
10-Bit, 45Msps, Full-Duplex Analog Front-End MAX19713
5.5 CLOCK-CYCLE LATENCY (QA) 5 CLOCK-CYCLE LATENCY (IA)
IA
QA tCL CLK
tCLK tCH
tDOQ D0-D9 D0Q D1I
tDOI D1Q D2I D2Q D3I D3Q D4I D4Q D5I D5Q D6I D6Q
Figure 3. Rx ADC System Timing Diagram
Table 2. Tx DAC Output Voltage vs. Input Codes
(Internal Reference Mode VREFDAC = 1.024V, External Reference Mode VREFDAC = VREFIN, VFS = 400 for 800mVP-P Full Scale)
DIFFERENTIAL OUTPUT VOLTAGE (V) OFFSET BINARY (DA0-DA9) 11 1111 1111 11 1111 1110 10 0000 0001 10 0000 0000 01 1111 1111 00 0000 0001 00 0000 0000 INPUT DECIMAL CODE 1023 1022 513 512 511 1 0
(VFS ) VREFDAC x 1023 1024 1023 (VFS ) VREFDAC 1024 (VFS ) VREFDAC 1024 (VFS ) VREFDAC 1024 (VFS ) -VREFDAC 1024 (VFS ) -VREFDAC 1024 (VFS ) -VREFDAC 1024
x x x x x x 1021 1023 3 1023 1 1023 1 1023 1021 1023 1023 1023
The Tx DAC outputs (IDN, IDP, QDN, QDP) are biased at an adjustable common-mode DC level and designed to drive a differential input stage with 70k input impedance. This simplifies the analog interface between RF quadrature upconverters and the MAX19713. Many RF upconverters require a 0.71V to 1.06V common-mode bias. The MAX19713 common-mode DC bias eliminates discrete level-setting resistors and code-generated level shifting while preserving the full dynamic range of each Tx DAC. The Tx DAC differential analog outputs cannot be used in single-ended mode because of the
18
internally generated common-mode DC level. Table 2 shows the Tx DAC output voltage vs. input codes. Table 10 shows the selection of DC common-mode levels. See Figure 4 for an illustration of the Tx DAC analog output levels. The Tx DAC also features an independent DC offset trim on each ID-QD channel. This feature is configured through the SPI interface. The DC offset correction is used to optimize sideband and carrier suppression in the Tx signal path (see Table 9).
______________________________________________________________________________________
10-Bit, 45Msps, Full-Duplex Analog Front-End MAX19713
MAX19713
EXAMPLE: Tx DAC CH-ID 0 90 Tx DAC CH-QD Tx RFIC INPUT REQUIREMENTS * DC COMMON-MODE BIAS = 0.9V (MIN), 1.3V (TYP) * BASEBAND INPUT = 400mV DC-COUPLED
FULL SCALE = 1.26V
VCOMD = 1.06V
COMMON-MODE LEVEL
SELECT CM1 = 0, CM0 = 0 VCOMD = 1.06V VFS = 400mV ZERO SCALE = 0.86V 0V
Figure 4. Tx DAC Common-Mode DC Level at IDN, IDP or QDN, QDP Differential Outputs
CLK tDSQ D0-D9 Q: N - 2 I: N - 1 tDSI tDHQ Q: N - 1 I: N tDHI Q: N I: N + 1
ID
N-2
N-1
N
QD
N-2
N-1
N
Figure 5. Tx DAC System Timing Diagram
______________________________________________________________________________________ 19
10-Bit, 45Msps, Full-Duplex Analog Front-End MAX19713
Tx DAC Timing Figure 5 shows the relationship among the clock, input data, and analog outputs. Channel ID data is latched on the falling edge of the clock signal, and channel QD data is latched on the rising edge of the clock signal, at which point both ID and QD outputs are simultaneously updated.
for faster enable and switching between shutdown, idle, and standby states as well as switching between FAST, SLOW, Rx and Tx modes and the FD mode. The WAKEUP-SEL register selects the operating mode that the MAX19713 is to enter immediately after coming out of shutdown (Table 11). See the Wake-Up Function section for more information. Shutdown mode offers the most dramatic power savings by shutting down all the analog sections (including the reference) of the MAX19713. In shutdown mode, the Rx ADC digital outputs are in tri-state mode, the Tx DAC digital inputs are internally pulled to OVDD, and the Tx DAC outputs are at 0V. When the Rx ADC outputs transition from tri-state to active mode, the last converted word is placed on the digital output bus. The Tx DAC previously stored data is lost when coming out of shutdown mode. The wake-up time from shutdown mode is dominated by the time required to charge the capacitors at REFP, REFN, and COM. In internal reference mode and buffered external reference mode, the wake-up time is typically 500s to enter Rx mode, 26.4s to enter Tx mode, and 500s to enter FD mode. In all operating modes, the Tx DAC inputs DA0-DA9 are internally pulled to OVDD. To reduce the supply current of the MAX19713 in shutdown mode do not pull DA0-DA9 low. This consideration is especially important in shutdown mode to achieve the lowest quiescent current. In idle mode, the reference and clock distribution circuits are powered, but all other functions are off. The Rx ADC outputs AD0-AD9 are forced to tri-state. The Tx DAC DA0-DA9 inputs are internally pulled to OVDD, while the Tx DAC outputs are at 0V. The wake-up time is 3.7s to enter Rx mode, 5.1s to enter Tx mode, and 5.1s to enter FD mode. When the Rx ADC outputs transition from tri-state to active, the last converted word is placed on the digital output bus. In standby mode, the reference is powered but all other device functions are off. The wake-up time from standby mode is 3.8s to enter Rx mode, 24.4s to enter Tx mode, and 24.4s to enter FD mode. When the Rx ADC outputs transition from tri-state to active, the last converted word is placed on the digital output bus.
3-Wire Serial Interface and Operation Modes
The 3-wire serial interface controls the MAX19713 operation modes as well as the three 12-bit aux-DACs and the 10-bit aux-ADC. Upon power-up, program the MAX19713 to operate in the desired mode. Use the 3wire serial interface to program the device for shutdown, idle, standby, FD, Rx, Tx, aux-DAC controls, or aux-ADC conversion. A 16-bit data register sets the mode control as shown in Table 3. The 16-bit word is composed of four control bits (A3-A0) and 12 data bits (D11-D0). Data is shifted in MSB first (D11) and LSB last (A0) format. Table 4 shows the MAX19713 power-management modes. Table 5 shows the SPI-controlled Tx, Rx, and FD modes. The serial interface remains active in all modes.
SPI Register Description Program the control bits, A3-A0, in the register as shown in Table 3 to select the operating mode. Modify A3-A0 bits to select from ENABLE-16, Aux-DAC1, Aux-DAC2, Aux-DAC3, IOFFSET, QOFFSET, COMSEL, Aux-ADC, ENABLE-8, and WAKEUP-SEL modes. ENABLE-16 is the default operating mode (see Table 6). This mode allows for shutdown, idle, and standby states as well as switching between FAST, SLOW, Rx and Tx modes. Tables 4 and 5 show the required SPI settings for each mode.
In ENABLE-16 mode, the aux-DACs have independent control bits E4, E5, and E6, bit E9 enables the aux-ADC. Table 7 shows the auxiliary DAC enable codes. Table 8 shows the auxiliary ADC enable code. Bits E11 and E10 are reserved. Program bits E11 and E10 to logic-low. Bits E3, E7, and E8 are not used. Modes aux-DAC1, aux-DAC2, and aux-DAC3 select the aux-DAC channels named DAC1, DAC2, and DAC3 and hold the data inputs for each DAC. Bits _D11-_D0 are the data inputs for each aux-DAC and can be programmed through SPI. The MAX19713 also includes two 6-bit registers that can be programmed to adjust the offsets for the Tx DAC ID and QD channels independently (see Table 9). Use the COMSEL mode to select the output common-mode voltage with bits CM1 and CM0 (see Table 10). Use aux-ADC mode to start the auxiliary ADC conversion (see the 10-Bit, 333ksps Auxiliary ADC section for details). Use ENABLE-8 mode
FAST and SLOW Rx and Tx Modes The MAX19713 features FAST and SLOW modes for switching between Rx and Tx operation. In FAST Tx mode, the Rx ADC core is powered on but the ADC digital outputs AD0-AD9 are tri-stated. The Tx DAC digital bus is active and the DAC core is fully operational.
20
______________________________________________________________________________________
10-Bit, 45Msps, Full-Duplex Analog Front-End MAX19713
Table 3. MAX19713 Mode Control
REGISTER NAME ENABLE-16 Aux-DAC1 Aux-DAC2 Aux-DAC3 IOFFSET QOFFSET COMSEL Aux-ADC ENABLE-8 WAKEUP-SEL D11 (MSB) E11 = 0 Reserved 1D11 2D11 3D11 -- -- -- AD11 = 0 Reserved -- -- D10 15 E10 = 0 Reserved 1D10 2D10 3D10 -- -- -- AD10 -- -- D9 14 E9 1D9 2D9 3D9 -- -- -- AD9 -- -- D8 13 -- 1D8 2D8 3D8 -- -- -- AD8 -- -- D7 12 -- 1D7 2D7 3D7 -- -- -- AD7 -- -- D6 11 E6 1D6 2D6 3D6 -- -- -- AD6 -- -- D5 10 E5 1D5 2D5 3D5 IO5 -- AD5 -- -- D4 9 E4 1D4 2D4 3D4 IO4 -- AD4 -- -- D3 8 -- 1D3 2D3 3D3 IO3 -- AD3 -- -- D2 7 E2 1D2 2D2 3D2 IO2 -- AD2 E2 W2 D1 6 E1 1D1 2D1 3D1 IO1 D0 5 E0 1D0 2D0 3D0 IO0 A3 4 0 0 0 0 0 0 0 0 1 1 A2 3 0 0 0 0 1 1 1 1 0 0 A1 2 0 0 1 1 0 0 1 1 0 0 A0 1 (LSB) 0 1 0 1 0 1 0 1 0 1
QO5 QO4 QO3 QO2 QO1 QO0 CM1 CM0 AD1 E1 W1 AD0 E0 W0
-- = Not used.
Table 4. Power-Management Modes
ADDRESS A3 A2 A1 A0 E9* DATA BITS MODE E2 E1 E0 FUNCTION (POWER MANAGEMENT) DESCRIPTION COMMENT
1
0
0
0
SHDN
SHUTDOWN
Rx ADC = OFF Tx DAC = OFF (TX DAC outputs at 0V) Aux-DAC = OFF Aux-ADC = OFF CLK = OFF REF = OFF Rx ADC = OFF Tx DAC = OFF (TX DAC outputs at 0V) Aux-DAC = Last State CLK = ON REF = ON Rx ADC = OFF Tx DAC = OFF (TX DAC outputs at 0V) Aux-DAC = Last State CLK = OFF REF = ON
Device is in complete shutdown.
0000 (16-Bit Mode) or 1000 (8-Bit Mode)
X**
0
0
1
IDLE
IDLE
Fast turn-on time. Moderate idle power.
X**
0
1
0
STBY
STANDBY
Slow turn-on time. Low standby power.
X = Don't care. *Bit E9 is not available in 8-bit mode. **In IDLE and STBY modes, the aux-ADC can be turned on or off.
______________________________________________________________________________________
21
10-Bit, 45Msps, Full-Duplex Analog Front-End MAX19713
Table 5. MAX19713 Tx, Rx, and FD Control Using SPI Commands
ADDRESS A3 A2 A1 A0 DATA BITS E2 E1 E0 MODE FUNCTION (Tx-Rx SWITCHING SPEED) DESCRIPTION Rx Mode: Rx ADC = ON Rx Bus = Enabled Tx DAC = OFF (Tx DAC outputs at 0V) Tx Bus = OFF (all inputs are pulled high) Tx Mode: Rx ADC = OFF Rx Bus = Tri-state Tx DAC = ON Tx Bus = ON Rx Mode: Rx ADC = ON Rx Bus = Enabled Tx DAC = ON (Tx DAC outputs at midscale) Tx Bus = OFF (all inputs are pulled high) Tx Mode: Rx ADC = ON Rx Bus = Tri-state Tx DAC = ON Tx Bus = ON FD Mode: Rx ADC = ON Rx Bus = ON Tx DAC = ON Tx Bus = ON COMMENT
0
1
1
SPI1-Rx
SLOW
Slow transition to Tx mode from this mode. Low power.
1
0
0
SPI2-Tx
SLOW
Slow transition to Rx mode from this mode. Low power.
0000 (16-Bit Mode) and 1000 (8-Bit Mode)
1
0
1
SPI3-Rx
FAST
Fast transition to Tx mode from this mode. Moderate power.
1
1
0
SPI4-Tx
FAST
Fast transition to Rx mode from this mode. Moderate power. Default Mode Fast transition to any mode. Moderate power.
1
1
1
FD
FAST
In FAST Rx mode, the Tx DAC core is powered on. The Tx DAC outputs are set to midscale. In this mode, the Tx DAC input bus is disconnected from the DAC core and DA0-DA9 are internally pulled to OVDD. The Rx ADC digital bus is active and the ADC core is fully operational. In FAST mode, the switching time from Tx to Rx, or Rx to Tx is minimized because the converters are on and do not have to recover from a power-down state. In FAST mode, the switching time from Rx to Tx and Tx to Rx is 0.1s. Power consumption is higher in FAST mode because both Tx and Rx cores are always on. In SLOW Tx mode, the Rx ADC core is powered off and the ADC digital outputs AD0-AD9 are tri-stated. The Tx
DAC digital bus is active and the DAC core is fully operational. In SLOW Rx mode, the Tx DAC core is powered off. The Tx DAC outputs are set to 0. In SLOW Rx mode, the Tx DAC input bus is disconnected from the DAC core and DA0-DA9 are internally pulled to OVDD. The Rx ADC digital bus is active and the ADC core is fully operational. The switching times for SLOW modes are 4.9s for Rx to Tx and 3.7s for Tx to Rx. Power consumption in SLOW Tx mode is 49.5mW, and 79.2mW in SLOW Rx mode. Power consumption in FAST Tx mode is 89.1mW, and 86.4mW in FAST Rx mode.
22
______________________________________________________________________________________
10-Bit, 45Msps, Full-Duplex Analog Front-End MAX19713
Table 6. MAX19713 Default (Power-On) Register Settings
REGISTER NAME D11 16 (MSB) 0 0 0 0 D10 15 D9 14 0 ENABLE-16 0 1 0 0 Aux-ADC = ON 1 0 0 -- 0 0 0 -- 1 0 0 D8 13 D7 12 D6 11 0 D5 10 0 D4 9 0 -- 1 0 0 0 0 1 0 0 0 0 D3 8 D2 7 1 D1 6 1 FD mode 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D0 5 1
Aux-DAC1 to Aux-DAC3 = ON 0 0 0 0 0 0 0 0 0 0 0 0 0 DAC1 output set to 1.1V DAC2 output set to 0V DAC3 output set to 0V
Aux-DAC1 Aux-DAC2 Aux-DAC3 IOFFSET QOFFSET COMSEL
-- -- --
-- -- -- 0
-- -- -- 0
-- -- -- 0
-- -- -- 0
-- -- -- 0
No offset on channel ID No offset on channel QD -- 0 -- 0 -- 0 -- 0 VCOMD = 1.06V
Aux-ADC
0
Aux-ADC = ON, Conversion = IDLE, Aux-ADC REF = 2.048V, MUX = ADC1, Averaging = 1, Clock Divider = 1, DOUT = Disabled -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 1 1 FD mode 1 1 Wake-up state = FD mode 1
ENABLE-8 WAKEUP-SEL
-- --
Table 7. Aux-DAC Enable Table (ENABLE-16 Mode)
E6 0 0 0 0 1 1 1 1 0 E5 0 0 1 1 0 0 1 1 0 E4 0 1 0 1 0 1 0 1 0 Aux-DAC3 ON ON ON ON OFF OFF OFF OFF Aux-DAC2 ON ON OFF OFF ON ON OFF OFF Default mode Aux-DAC1 ON OFF ON OFF ON OFF ON OFF
Table 8. Aux-ADC Enable Table (ENABLE-16 Mode)
E9 0 (Default) 1 SELECTION Aux-ADC is Powered ON Aux-ADC is Powered OFF
FD Mode The MAX19713 features an FD mode, which is ideal for applications supporting frequency-division duplex. In FD mode, both Rx ADC and Tx DAC, as well as their respective digital buses, are active and the device can receive and transmit simultaneously. Switching from FD mode to other Rx or Tx modes is fast (0.1s) since
______________________________________________________________________________________
23
10-Bit, 45Msps, Full-Duplex Analog Front-End MAX19713
Table 9. Offset Control Bits for ID and QD Channels (IOFFSET or QOFFSET Mode)
BITS IO5-IO0 WHEN IN IOFFSET MODE, BITS QO5-QO0 WHEN IN QOFFSET MODE IO5/QO5 1 1 1
* * *
IO4/QO4 1 1 1
* * *
IO3/QO3 1 1 1
* * *
IO2/QO2 1 1 1
* * *
IO1/QO1 1 1 0
* * *
IO0/QO0 1 0 1
* * *
OFFSET 1 LSB = (VFSP-P / 1023) -31 LSB -30 LSB -29 LSB
* * *
1 1 1 0 0 0
* * *
0 0 0 0 0 0
* * *
0 0 0 0 0 0
* * *
0 0 0 0 0 0
* * *
1 0 0 0 0 1
* * *
0 1 0 0 1 0
* * *
-2 LSB -1 LSB 0mV 0mV (Default) 1 LSB 2 LSB
* * *
0 0 0
1 1 1
1 1 1
1 1 1
0 1 1
1 0 1
29 LSB 30 LSB 31 LSB
Note: 1 LSB = (800mVP-P / 1023) = 0.782mV.
Table 10. Common-Mode Select (COMSEL Mode)
CM1 0 0 1 1 CM0 0 1 0 1 Tx PATH OUTPUT COMMON MODE (V) 1.06 (Default) 0.94 0.82 0.71
Table 11. WAKEUP-SEL Register
W2 W1 W0 POWER MODE AFTER WAKE-UP (WAKE-UP STATE) Invalid Value. This value is ignored when inadvertently written to the WAKEUP-SEL register. IDLE STBY SPI1-SLOW Rx SPI2-SLOW Tx SPI3-FAST Rx SPI4-FAST Tx FD (Default)
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
the on-board converters are already powered. Consequently, power consumption in this mode is the maximum of all operating modes. In FD mode the MAX19713 consumes 91.8mW.
Wake-Up Function The MAX19713 uses the SPI interface to control the operating modes of the device including the shutdown and wake-up functions. Once the device has been placed in shutdown through the appropriate SPI command, the first pulse on CS/WAKE performs a wake-up function. At the first rising edge of CS/WAKE, the MAX19713 is forced to a preset operating mode determined by the WAKEUP-SEL register. This mode is
24
termed the wake-up state. If the WAKEUP-SEL register has not been programmed, the wake-up state for the MAX19713 is FD mode by default (Tables 6, 11). The WAKEUP-SEL register cannot be programmed with W2 = 0, W1 = 0, and W0 = 0. If this value is inadvertently written to the device, it is ignored and the register continues to store its previous value. Upon wake-up, the
______________________________________________________________________________________
10-Bit, 45Msps, Full-Duplex Analog Front-End MAX19713
tCSW CS/WAKE tCSS SCLK tCH tDS DIN MSB tDH LSB tCL tCP tCS
Figure 6. Serial-Interface Timing Diagram
CS/WAKE
SCLK
DIN
16-BIT SERIAL DATA INPUT
AD0-AD9
ADC DIGITAL OUTPUT SINAD SETTLES TO WITHIN 1dB tWAKE,SD,ST_ TO Rx MODE OR tENABLE,RX DAC ANALOG OUTPUT SETTLES TO 10 LSB ERROR tWAKE,SD,ST_ TO Tx MODE OR tENABLE,TX
ID/QD
Figure 7. Mode-Recovery Timing Diagram
MAX19713 enters the power mode determined by the WAKEUP-SEL register, however, all other settings (Tx DAC offset, Tx DAC common-mode voltage, aux-DAC settings, aux-ADC state) are restored to their values prior to shutdown. The only SPI line that is monitored by the MAX19713 during shutdown is CS/WAKE. Any information transmitted to the MAX19713 concurrent with the CS/WAKE wake-up pulse is ignored.
when CS/WAKE transitions high. CS/WAKE must transition high for a minimum of 80ns before the next write sequence. SCLK can idle either high or low between transitions. Figure 6 shows the detailed timing diagram of the 3-wire serial interface.
Mode-Recovery Timing
Figure 7 shows the mode-recovery timing diagram. tWAKE is the wake-up time when exiting shutdown, idle, or standby mode and entering Rx, Tx, or FD mode. tENABLE is the recovery time when switching between either Rx or Tx mode. tWAKE or tENABLE is the time for the Rx ADC to settle within 1dB of specified SINAD performance and Tx DAC settling to 10 LSB error. tWAKE and tENABLE times are measured after the 16-bit serial command is latched into the MAX19713 by a CS/WAKE transition high. In FAST mode, the recovery time is 0.1s to switch between Tx or Rx modes.
QSPI is a trademark of Motorola, Inc.
SPI Timing The serial digital interface is a standard 3-wire connection (CS/WAKE, SCLK, DIN) compatible with SPI/QSPITM/ MICROWIRE/DSP interfaces. Set CS/WAKE low to enable the serial data loading at DIN or output at DOUT. Following a CS/WAKE high-to-low transition, data is shifted synchronously, most significant bit first, on the rising edge of the serial clock (SCLK). After 16 bits are loaded into the serial input register, data is transferred to the latch
______________________________________________________________________________________
25
10-Bit, 45Msps, Full-Duplex Analog Front-End MAX19713
System Clock Input (CLK)
Both the Rx ADC and Tx DAC share the CLK input. The CLK input accepts a CMOS-compatible signal level set by OVDD from 1.8V to VDD. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (< 2ns). Specifically, sampling occurs on the rising edge of the clock signal, requiring this edge to provide the lowest possible jitter. Any significant clock jitter limits the SNR performance of the on-chip Rx ADC as follows: 1 SNR = 20 x log 2 x x fIN x t AJ where fIN represents the analog input frequency and tAJ is the time of the clock jitter. Clock jitter is especially critical for undersampling applications. Consider the clock input as an analog input and route away from any analog input or other digital signal lines. The MAX19713 clock input operates with an OVDD / 2 voltage threshold and accepts a 50% 10% duty cycle. When the clock signal is stopped at CLK input (CLK = 0 or OVDD), all internal registers hold their last value and the MAX19713 saves the last power-management mode or Tx/Rx/FD command. All converter circuits (Rx ADC, Tx DAC, aux-ADC, and aux-DACs) hold their last value. When the clock signal is restarted at CLK, allow 3.8s (clock wake-up time) for the internal clock circuitry to settle before updating the Tx DAC, reading a valid Rx ADC conversion result, or starting an aux-ADC conversion. This ensures the converters (Rx ADC, Tx DAC, aux-ADC) meet all dynamic performance specifications. The aux-DAC channels are not dependent on CLK, so they can be updated when CLK is idle. Loading on the aux-DAC outputs should be carefully observed to achieve the specified settling time and stability. The capacitive load must be kept to a maximum of 5pF including package and trace capacitance. The resistive load must be greater than 200k. If capacitive loading exceeds 5pF, then add a 10k resistor in series with the output. Adding the series resistor helps drive larger load capacitance (< 15pF) at the expense of slower settling time.
10-Bit, 333ksps Auxiliary ADC
The MAX19713 integrates a 333ksps, 10-bit aux-ADC with an input 4:1 multiplexer. In the aux-ADC mode register, setting bit AD0 begins a conversion with the auxiliary ADC. Bit AD0 automatically clears when the conversion is complete. Setting or clearing AD0 during a conversion has no effect (see Table 12). Bit AD1 determines the internal reference of the auxiliary ADC (see Table 13). Bits AD2 and AD3 determine the auxiliary ADC input source (see Table 14). Bits AD4, AD5, and AD6 select the number of averages taken when a single start-convert command is given. The conversion time increases as the number of averages increases (see Table 15). The conversion clock can be divided down from the system clock by properly setting bits AD7, AD8, and AD9 (see Table 16). The aux-ADC output data can be written out of DOUT by setting bit AD10 high (see Table 17). The aux-ADC features a 4:1 input multiplexer to allow measurements on four input sources. The input sources are selected by AD3 and AD2 (see Table 14). Two of the multiplexer inputs (ADC1 and ADC2) can be connected to external sources such as an RF power detector like the MAX2208 or temperature sensor like the MAX6613. The other two multiplexer inputs are internal connections to VDD and OVDD that monitor the powersupply voltages. The internal VDD and OVDD connections are made through integrated dividers that yield VDD / 2 and OVDD / 2 measurement results. The auxADC voltage reference can be selected between an internal 2.048V bandgap reference or VDD (see Table 13). The VDD reference selection is provided to allow measurement of an external voltage source with a fullscale range extending beyond the 2.048V level. The input source voltage range cannot extend above VDD. The conversion requires 12 clock edges (1 for input sampling, 1 for each of the 10 bits, and 1 at the end for loading into the serial output register) to complete one conversion cycle (when no averaging is being done). Each conversion of an average (when averaging is set greater than 1) requires 12 clock edges. The conversion clock is generated from the system clock input (CLK). An SPI-programmable divider divides the system
12-Bit, Auxiliary Control DACs
The MAX19713 includes three 12-bit aux-DACs (DAC1, DAC2, DAC3) with 1s settling time for controlling variable-gain amplifier (VGA), automatic gain-control (AGC), and automatic frequency-control (AFC) functions. The aux-DAC output range is 0.2V to 2.57V as defined by VOH - VOL. During power-up, the VGA and AGC outputs (DAC2 and DAC3) are at zero. The AFC DAC (DAC1) is at 1.1V during power-up. The aux-DACs can be independently controlled through the SPI bus, except during SHDN mode where the aux-DACs are turned off completely and the output voltage is set to zero. In STBY and IDLE modes the aux-DACs maintain the last value. On wake-up from SHDN, the aux-DACs resume the last values.
26
______________________________________________________________________________________
10-Bit, 45Msps, Full-Duplex Analog Front-End MAX19713
Table 12. Auxiliary ADC Convert
AD0 0 1 SELECTION Aux-ADC Idle (Default) Aux-ADC Start-Convert
Table 16. Auxiliary ADC Clock (CLK) Divider
AD9 0 0 0 0 1 1 1 1 AD8 0 0 1 1 0 0 1 1 AD7 0 1 0 1 0 1 0 1 Aux-ADC CONVERSION CLOCK CLK Divided by 1 (Default) CLK Divided by 2 CLK Divided by 4 CLK Divided by 8 CLK Divided by 16 CLK Divided by 32 CLK Divided by 64 CLK Divided by 128
Table 13. Auxiliary ADC Reference
AD1 0 1 SELECTION Internal 2.048V Reference (Default) Internal VDD Reference
Table 14. Auxiliary ADC Input Source
AD3 0 0 1 1 AD2 0 1 0 1 Aux-ADC INPUT SOURCE ADC1 (Default) ADC2 VDD / 2 OVDD / 2 1
Table 17. Auxiliary ADC Data Output Mode
AD10 0 SELECTION Aux-ADC Data is Not Available on DOUT (Default) Aux-ADC Enters Data Output Mode Where Data is Available on DOUT
Table 15. Auxiliary ADC Averaging
AD6 0 0 0 0 1 1 1 AD5 0 0 1 1 0 0 1 AD4 0 1 0 1 0 1 X Aux-ADC AVERAGING 1 Conversion (No Averaging) (Default) Average of 2 Conversions Average of 4 Conversions Average of 8 Conversions Average of 16 Conversions Average of 32 Conversions Average of 32 Conversions
Reading DOUT from the Aux-ADC
DOUT is normally in a high-impedance condition. Upon setting the auxiliary ADC start conversion bit (bit AD0), DOUT becomes active and goes high, indicating that the aux-ADC is busy. When the conversion cycle is complete (including averaging), the data is placed into an output register and DOUT goes low, indicating that the output data is ready to be driven onto DOUT. When bit AD10 is set (AD10 = 1), the aux-ADC enters a data output mode where data is available at DOUT on the next low assertion of CS/WAKE. The auxiliary ADC data is shifted out of DOUT (MSB first) with the data transitioning on the falling edge of the serial clock (SCLK). Since a DOUT read requires 16 bits, DOUT holds the value of the last conversion data bit for the last 6 bits (6 least significant bits) following the aux-ADC conversion data. DOUT enters a high-impedance state when CS/WAKE is deasserted high. When bit AD10 is cleared (AD10 = 0), the aux-ADC data is not available on DOUT (see Table 17). After the aux-ADC completes a conversion, the data result is loaded to an output register waiting to be shifted out. No further conversions are possible until data is shifted out. This means that if the first conversion command sets AD10 = 0, AD0 = 1, then it cannot be followed by conversion commands setting AD10 = 0, AD0 = 1 or AD10 = 1, AD0 = 1. If this sequence of commands is inadvertently used then DOUT is disabled. To resume normal operation set AD0 = 0.
27
X = Don't care.
clock by the appropriate divisor (set with bits AD7, AD8, and AD9; see Table 16) and provides the conversion clock to the auxiliary ADC. The auxiliary ADC has a maximum conversion rate of 333ksps. The maximum conversion clock frequency is 4MHz (333ksps x 12 clocks). Choose the proper divider value to keep the conversion clock frequency under 4MHz, based upon the system CLK frequency supplied to the MAX19713 (see Table 16). The total conversion time (tCONV) of the auxiliary ADC can be calculated as t CONV = (12 x N AVG x N DIV) / f CLK; where N AVG is the number of averages (see Table 15), NDIV is the CLK divisor (see Table 16), and fCLK is the system CLK frequency.
______________________________________________________________________________________
10-Bit, 45Msps, Full-Duplex Analog Front-End MAX19713
The fastest method to perform sequential conversions with the aux-ADC is by sending consecutive commands setting AD10 = 1, AD0 = 1. With this sequence the CS/WAKE falling edge shifts data from the previous conversion on to DOUT and the rising edge of CS/WAKE
1. SINGLE AUX-ADC CONVERSION WITH CONVERSION DATA READOUT AT A LATER TIME tCSD tCD tCHZ
loads the next conversion command at DIN. Allow enough time for each conversion to complete before sending the next conversion command. See Figure 8 for single and continuous conversion examples.
CS/WAKE
SCLK DIN DOUT
1 0 0 1 0 1 1
16 1
1
16
1 0 1 0 0 1 1
16 1
1
10
11
16
DIN SET HIGH DURING SINGLE READ D9 D1 D0 D0 HELD
AD10 = 0, AD0 = 1, PERFORM CONVERSION, DOUT DISABLED AUX-ADC REGISTER ADDRESS
DOUT TRANSITIONS FROM HIGH IMPEDANCE TO LOGICHIGH INDICATING START OF CONVERSION DOUT TRANSITIONS LOW INDICATING END OF CONVERSION, DATA IS AVAILABLE AND CAN BE SHIFTED OUT IF DOUT IS ENABLED, AD0 CLEARED
IF AUX-ADC CONVERSION DOES NOT NEED TO BE READ IMMEDIATELY, THE SPI INTERFACE IS FREE AND CAN BE USED FOR OTHER FUNCTIONS, SUCH AS HOUSEKEEPING AUX-DAC ADJUSTMENT, ETC.
AUX-ADC REGISTER ADDRESS FIRST FALLING EDGE OF CS/WAKE AFTER DOUT IS ENABLED STARTS SHIFTING THE AUX-ADC CONVERSION DATA ON THE FALLING EDGE OF SCLK 10-BIT AUX-ADC CONVERSION RESULT IS SHIFTED OUT ON DOUT ON THE FALLING EDGE OF SCLK MSB FIRST
CONVERSION RESULT DATA BIT D0 IS HELD FOR THE SIX LEAST SIGNIFICANT BITS
DOUT TRANSITIONS TO HIGH IMPEDANCE
AD10 = 1, AD0 = 0, AUX-ADC IDLE (NO CONVERSION), DOUT ENABLED AND CONVERSION DATA IS SHIFTED OUT ON NEXT CS/WAKE FALLING EDGE
2. CONTINUOUS AUX-ADC CONVERSIONS tCONV CS/WAKE tDCS SCLK DIN DOUT 1 0 0 1 0 1 1 16 1 1 0 1 D9 D1 D0 10 11 12 1 13 0 14 1 15 1 16 1 1 0 1 D9 D1 D0 10 11 12 1 13 0 14 1 15 1 16 1
D0 HELD
D0 HELD
AD10 = 1, AD0 = 1, PERFORM CONVERSION, DOUT ENABLED AUX-ADC REGISTER ADDRESS DOUT TRANSITIONS FROM HIGH IMPEDANCE TO LOGICHIGH INDICATING START OF FIRST CONVERSION DOUT TRANSITIONS LOW INDICATING END OF FIRST CONVERSION, DATA IS AVAILABLE AND CAN BE SHIFTED OUT IF DOUT IS ENABLED, AD0 CLEARED
AD10 = 1, AD0 = 1, PERFORM CONVERSION, DOUT ENABLED FIRST 10-BIT AUX-ADC CONVERSION RESULT IS SHIFTED OUT ON DOUT ON THE FALLING EDGE OF SCLK MSB FIRST DOUT TRANSITIONS HIGH INDICATING START OF SECOND CONVERSION DOUT TRANSITIONS LOW INDICATING END OF SECOND CONVERSION, DATA IS AVAILABLE AND CAN BE SHIFTED OUT IF DOUT IS ENABLED, AD0 CLEARED
AD10 = 1, AD0 = 1, PERFORM CONVERSION, DOUT ENABLED SECOND 10-BIT AUX-ADC CONVERSION RESULT IS SHIFTED OUT ON DOUT ON THE FALLING EDGE OF SCLK MSB FIRST DOUT TRANSITIONS HIGH INDICATING START OF THIRD CONVERSION DOUT TRANSITIONS LOW INDICATING END OF THIRD CONVERSION, DATA IS AVAILABLE AND CAN BE SHIFTED OUT IF DOUT IS ENABLED, AD0 CLEARED
Figure 8. Aux-ADC Conversions Timing
28 ______________________________________________________________________________________
10-Bit, 45Msps, Full-Duplex Analog Front-End
DIN can be written independent of DOUT state. A 16-bit instruction at DIN updates the device configuration. To prevent modifying internal registers while reading data from DOUT, hold DIN at a high state (only applies if sequential aux-ADC conversions are not executed). This effectively writes all ones into address 1111. Since address 1111 does not exist, no internal registers are affected.
Reference Configurations
The MAX19713 features an internal precision 1.024Vbandgap reference that is stable over the entire powersupply and temperature ranges. The REFIN input provides two modes of reference operation. The voltage at REFIN (VREFIN) sets the reference operation mode (Table 18). In internal reference mode, connect REFIN to V DD . VREF is an internally generated 0.512V 4% reference level. COM, REFP, and REFN are low-impedance outputs with VCOM = VDD / 2, VREFP = VDD / 2 + VREF / 2, and VREFN = VDD / 2 - VREF / 2. Bypass REFP, REFN, and COM each with a 0.33F capacitor. Bypass REFIN to GND with a 0.1F capacitor. In buffered external reference mode, apply 1.024V 10% at REFIN. In this mode, COM, REFP, and REFN are low-impedance outputs with V COM = V DD / 2, VREFP = VDD / 2 + VREFIN / 4, and VREFN = VDD / 2 VREFIN / 4. Bypass REFP, REFN, and COM each with a 0.33F capacitor. Bypass REFIN to GND with a 0.1F capacitor. In this mode, the Tx DAC full-scale output is proportional to the external reference. For example, if the VREFIN is increased by 10% (max), the Tx DAC fullscale output is also increased by 10% or 440mV.
MAX19713
25 IAP 0.1F VIN COM 0.33F 0.1F 22pF
IAN 25 22pF
MAX19713
25 QAP 0.1F VIN 22pF
Applications Information
Using Balun Transformer AC-Coupling
An RF transformer (Figure 9) provides an excellent solution to convert a single-ended signal source to a fully differential signal for optimum ADC performance. Connecting the center tap of the transformer to COM provides a VDD / 2 DC level shift to the input. A 1:1 transformer can be used, or a step-up transformer can be selected to reduce the drive requirements. In general, the MAX19713 provides better SFDR and THD with fully differential input signals than single-ended signals, especially for high input frequencies. In differential mode, even-order harmonics are lower as both inputs (IAP, IAN, QAP, QAN) are balanced, and each of the
0.33F
0.1F
QAN 25 22pF
Figure 9. Balun Transformer-Coupled Single-Ended-toDifferential Input Drive for Rx ADC
Table 18. Reference Modes
VREFIN > 0.8V x VDD REFERENCE MODE Internal Reference Mode. VREF is internally generated to be 0.512V. Bypass REFP, REFN, and COM each with a 0.33F capacitor. Buffered External Reference Mode. An external 1.024V 10% reference voltage is applied to REFIN. VREF is internally generated to be VREFIN / 2. Bypass REFP, REFN, and COM each with a 0.33F capacitor. Bypass REFIN to GND with a 0.1F capacitor.
1.024V 10%
______________________________________________________________________________________
29
10-Bit, 45Msps, Full-Duplex Analog Front-End MAX19713
Rx ADC inputs only requires half the signal swing compared to single-ended mode. Figure 10 shows an RF transformer converting the MAX19713 Tx DAC differential analog outputs to single-ended.
IDP VOUT
Using Op-Amp Coupling
Drive the MAX19713 Rx ADC with op amps when a balun transformer is not available. Figures 11 and 12 show the Rx ADC being driven by op amps for AC-coupled single-ended and DC-coupled differential applications. Amplifiers such as the MAX4454 and MAX4354 provide high speed, high bandwidth, low noise, and low distortion to maintain the input signal integrity. The op-amp circuit shown in Figure 12 can also be used to interface with the Tx DAC differential analog outputs to provide gain or buffering. The Tx DAC differential analog outputs cannot be used in single-ended mode because of the internally generated common-mode level. Also, the Tx DAC analog outputs are designed to drive a differential input stage with input impedance 70k. If single-ended outputs are desired, use an amplifier to provide differential-to-single-ended conversion and select an amplifier with proper input commonmode voltage range.
MAX19713
IDN
QDP
VOUT
QDN
Figure 10. Balun Transformer-Coupled Differential-to-SingleEnded Output Drive for Tx DAC
REFP
FDD Application
Figure 13 illustrates a typical FDD application circuit. The MAX19713 interfaces directly with the radio front-ends to provide a complete "RF-to-Bits" solution for FDD applications such as 802.11, 802.16, WCDMA, and proprietary radio systems. The MAX19713 provides several system benefits to digital baseband developers: * Fast Time-to-Market * * * * * * High-Performance, Low-Power Analog Functions Low-Risk, Proven Analog Front-End Solution No Mixed-Signal Test Times No NRE Charges No IP Royalty Charges Enables Digital Baseband and Scale with 65nm to 90nm CMOS
VIN
1k 0.1F
RISO 50 IAP CIN 22pF
100
1k
COM REFN 0.1F RISO 50 100 IAN CIN 22pF REFP
MAX19713
RISO 50 QAP CIN 22pF
VIN
0.1F
1k
Grounding, Bypassing, and Board Layout
The MAX19713 requires high-speed board layout design techniques. Refer to the MAX19713 EV kit data sheet for a board layout reference. Place all bypass capacitors as close to the device as possible, preferably on the same side of the board as the device, using surface-mount devices for minimum inductance. Bypass VDD to GND with a 0.1F ceramic capacitor in parallel with a 2.2F capacitor. Bypass OVDD to OGND with a 0.1F ceramic
30
100
1k
REFN
0.1F RISO 50
100
QAN CIN 22pF
Figure 11. Single-Ended Drive for Rx ADC
______________________________________________________________________________________
10-Bit, 45Msps, Full-Duplex Analog Front-End MAX19713
R4 600
R5 600
R1 600
RISO 22 IAN CIN 5pF
R2 600 R6 600 R3 600 R8 600 R7 600 R9 600 COM
MAX19713
RISO 22 CIN 5pF IAP
R10 600
R11 600
Figure 12. Rx ADC DC-Coupled Differential Drive
capacitor in parallel with a 2.2F capacitor. Bypass REFP, REFN, and COM each to GND with a 0.33F ceramic capacitor. Bypass REFIN to GND with a 0.1F capacitor. Multilayer boards with separated ground and power planes yield the highest level of signal integrity. Use a split ground plane arranged to match the physical location of the analog ground (GND) and the digital outputdriver ground (OGND) on the device package. Connect the MAX19713 exposed backside paddle to the GND plane. Join the two ground planes at a single point so the noisy digital ground currents do not interfere with the analog ground plane. The ideal location for this connection can be determined experimentally at a point along the gap between the two ground planes. Make this connection with a low-value, surface-mount resistor (1 to 5), a ferrite bead, or a direct short. Alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated
from any noisy digital system's ground plane (e.g., downstream output buffer or DSP ground plane). Route high-speed digital signal traces away from sensitive analog traces. Make sure to isolate the analog input lines to each respective converter to minimize channel-to-channel crosstalk. Keep all signal lines short and free of 90 turns.
Dynamic Parameter Definitions
ADC and DAC Static Parameter Definitions
Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the device are measured using the best-straight-line fit (DAC Figure 14a).
______________________________________________________________________________________
31
10-Bit, 45Msps, Full-Duplex Analog Front-End MAX19713
VDD = 2.7V TO 3.3V OVDD = 1.8V TO VDD
IAP 10-BIT ADC IAN QAP 10-BIT ADC FDD ZIF TRANSCEIVER QAN IDP 10-BIT DAC IDN QDP AGC QDN 10-BIT DAC SYSTEM CLOCK PROGRAMMABLE OFFSET/CM DAC1 TCXO 12-BIT AUX-DAC DATA MUX DATA MUX
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9
DIGITAL BASEBAND ASIC
CLK
SERIAL INTERFACE AND SYSTEM CONTROL
CS/WAKE SCLK DIN
DAC2
12-BIT AUX-DAC
DOUT 1.024V REFERENCE BUFFER REFIN REFP COM REFN
DAC3
12-BIT AUX-DAC
ADC1 BATTERY VOLTAGE MONITOR TEMPERATURE MEASUREMENT ADC2 VDD / 2 OVDD / 2 10-BIT AUX-ADC
MAX19713
GND
OGND
Figure 13. Typical FDD Radio Application Circuit
32
______________________________________________________________________________________
10-Bit, 45Msps, Full-Duplex Analog Front-End
Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes (ADC) and a monotonic transfer function (ADC and DAC) (DAC Figure 14b). ADC Offset Error Ideally, the midscale transition occurs at 0.5 LSB above midscale. The offset error is the amount of deviation between the measured transition point and the ideal transition point. DAC Offset Error Offset error (Figure 14a) is the difference between the ideal and actual offset point. The offset point is the output value when the digital input is midscale. This error affects all codes by the same amount and usually can be compensated by trimming. ADC Gain Error Ideally, the ADC full-scale transition occurs at 1.5 LSB below full scale. The gain error is the amount of deviation between the measured transition point and the ideal transition point with the offset error removed.
MAX19713
7 6 ANALOG OUTPUT VALUE 5 4 3 2 1 0 000 001 010 011 100 101 110 111 DIGITAL INPUT CODE AT STEP 001 (0.25 LSB) AT STEP 011 (0.5 LSB)
Figure 14a. Integral Nonlinearity
6 ANALOG OUTPUT VALUE 5 4 3 1 LSB 2 1 0 000 001 010 011 100 101 DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR (+0.25 LSB) 1 LSB DIFFERENTIAL LINEARITY ERROR (-0.25 LSB)
ADC Dynamic Parameter Definitions
Aperture Jitter Figure 15 shows the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay. Aperture Delay Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (Figure 15). Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error) and results directly from the ADC's resolution (N bits):
SNR(max) = 6.02 x N + 1.76 (in dB) In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first five harmonics, and the DC offset.
Figure 14b. Differential Nonlinearity
CLK
ANALOG INPUT tAD tAJ SAMPLED DATA (T/H)
Signal-to-Noise and Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset.
T/H
TRACK
HOLD
TRACK
Figure 15. T/H Aperture Timing
33
______________________________________________________________________________________
10-Bit, 45Msps, Full-Duplex Analog Front-End MAX19713
Effective Number of Bits (ENOB) ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. ENOB for a full-scale sinusoidal input waveform is computed from:
ENOB = (SINAD - 1.76) / 6.02
Power-Supply Rejection Power-supply rejection is defined as the shift in offset and gain error when the power supply is changed 5%. Small-Signal Bandwidth A small -20dBFS analog input signal is applied to an ADC in such a way that the signal's slew rate does not limit the ADC's performance. The input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by 3dB. Note that the T/H performance is usually the limiting factor for the small-signal input bandwidth. Full-Power Bandwidth A large -0.5dBFS analog input signal is applied to an ADC, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by 3dB. This point is defined as the fullpower bandwidth frequency.
Total Harmonic Distortion (THD) THD is typically the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as:
(V22 + V32 + V42 + V52 + V62 THD = 20 x log V1 )
where V1 is the fundamental amplitude and V2-V6 are the amplitudes of the 2nd- through 6th-order harmonics.
Third Harmonic Distortion (HD3) HD3 is defined as the ratio of the RMS value of the third harmonic component to the fundamental input signal. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest spurious component, excluding DC offset. Intermodulation Distortion (IMD) IMD is the total power of the intermodulation product relative to the total input power when two tones, fIN1 and fIN2, are present at the inputs. The intermodulation products are (fIN1 fIN2), (2 x fIN1), (2 x fIN2), (2 x fIN1 fIN2), (2 x fIN2 fIN1). The individual input tone levels are at -7dBFS. 3rd-Order Intermodulation (IM3) IM3 is the power of the worst 3rd-order intermodulation product relative to the input power of either input tone when two tones, fIN1 and fIN2, are present at the inputs. The 3rd-order intermodulation products are (2 x fIN1 fIN2), (2 fIN2 fIN1). The individual input tone levels are at -7dBFS.
DAC Dynamic Parameter Definitions
Total Harmonic Distortion THD is the ratio of the RMS sum of the output harmonics up to the Nyquist frequency divided by the fundamental:
(V22 + V32 + ...+ Vn2 ) THD = 20 x log V1
where V1 is the fundamental amplitude and V2 through Vn are the amplitudes of the 2nd through nth harmonic up to the Nyquist frequency.
Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio of RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distortion component up to the Nyquist frequency excluding DC.
Selector Guide
PART MAX19710 MAX19711 MAX19712 MAX19713 SAMPLING RATE (Msps) 7.5 11 22 45 INTEGRATED CDMA Tx FILTERS No Yes No No
34
______________________________________________________________________________________
10-Bit, 45Msps, Full-Duplex Analog Front-End MAX19713
Functional Diagram
VDD = 2.7V TO 3.3V OVDD = 1.8V TO VDD
IAP IAN
10-BIT ADC DATA MUX
QAP QAN
10-BIT ADC
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9
IDP IDN
10-BIT DAC DATA MUX
QDP QDN
10-BIT DAC
SYSTEM CLOCK PROGRAMMABLE OFFSET/CM DAC1 12-BIT AUX-DAC
CLK
SERIAL INTERFACE AND SYSTEM CONTROL
CS/WAKE SCLK DIN
DAC2
12-BIT AUX-DAC 1.024V REFERENCE BUFFER
DOUT REFIN REFP REFN COM
DAC3
12-BIT AUX-DAC
ADC1 ADC2
10-BIT AUX-ADC VDD / 2 OVDD / 2
MAX19713
GND
OGND
______________________________________________________________________________________
35
10-Bit, 45Msps, Full-Duplex Analog Front-End MAX19713
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
E E/2
DETAIL A
(NE-1) X e
k e D/2
D
(ND-1) X e
C L
D2
D2/2
b L E2/2 k
C L
E2
C L
C L
L e e
L
A1
A2
A
PACKAGE OUTLINE 32, 44, 48, 56L THIN QFN, 7x7x0.8mm
21-0144
F
1
2
36
______________________________________________________________________________________
32, 44, 48L QFN.EPS
10-Bit, 45Msps, Full-Duplex Analog Front-End
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX19713
PACKAGE OUTLINE 32, 44, 48, 56L THIN QFN, 7x7x0.8mm
21-0144
F
2
2
Revision History
Pages changed at Rev 1: 1-4, 29, 37
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 37
(c) 2006 Maxim Integrated Products
Springer
is a registered trademark of Maxim Integrated Products, Inc.

▲Up To Search▲

Price & Availability of MAX19713ETN

	To Download MAX19713ETN Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .